AMD used today, November 10, 2026, to introduce its 6th-generation Zen 6 architecture, and the big headline is the company’s claim of an average 27% IPC gain over Zen 5 in selected server workloads.
According to AMD, that result comes from a same-clock comparison of 16 Zen 6c cores on a single chiplet against 16 Zen 5 cores split across two chiplets. The company also says the uplift across broader enterprise and cloud workloads lands closer to 20%.
The architectural changes are pretty straightforward on paper: a larger execution window, improved branch prediction, better integer scheduling, full AVX-512 FP16 support, Bit Matrix Multiply, and four VNNI-INT8 pipelines. Zen 6 is tuned for higher clock speeds, while Zen 6c is aimed at density. Both keep two threads per core and maintain ISA compatibility.
For desktop users, the more interesting shift may be in the CCD layout.
The standard CCD moves from 8 cores to 12 cores, while Zen 6c goes from 16 to 32. That could pave the way for a single-chiplet 12-core AMD Ryzen, 24-core dual-CCD parts, lower inter-chiplet latency in gaming, and more cache.
Cache goes up too. Zen 6 moves from 32MB to 48MB of shared L3 per chiplet, and Zen 6c jumps from 32MB to 128MB, with both landing at 4MB per core. If you’re waiting for the next big Ryzen leap, this is something to keep an eye on.
Zen 6 is showing up first in AMD’s 6th Gen EPYC 9006 Venice systems, which the company says are shipping now following the November 10, 2026 announcement. Those parts scale up to 8 chiplets, 96 Zen 6 cores or 256 Zen 6c cores, 5.3GHz high-frequency SKUs, PCIe 6.0, DDR5 MRDIMM support up to 12,800 MT/s, and, in AMD’s telling, industry ties to TSMC’s 2nm process.
What you still don’t have are official AMD Ryzen Zen 6 models, prices, release dates, or desktop benchmarks, even if Ryzen 10000 “Olympic Ridge” is still expected around 2027.
Author: Chema Carvajal Sarabia
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