AMD unveiled today, November 10, 2026, Zen 6, and the first batch is headed straight for the server market with the AMD EPYC 9006 “Venice”. On paper, at least from what the company has shown, the jump comes from packing more cores into each chiplet, increasing cache, and tweaking internal parts of the architecture to push IPC. What that will mean for future desktop AMD Ryzen remains, for now, more an expectation than a measured reality.
The figure that’s going to generate the most headlines is IPC. AMD speaks of an average improvement of 27% in Zen 6c over Zen 5, but here you have to look closely at how that number was obtained: AMD itself explains that it comes from a selection of server workloads, comparing 16 active Zen 6c cores inside a single chiplet with 16 Zen 5 cores spread across two chiplets and running at the same frequency. In enterprise and cloud scenarios, the gains AMD reports sit around 20%.
One clear change is in density per chiplet. Zen 6 goes from 8 to 12 cores per CCD, 50% more, while Zen 6c doubles that number and goes from 16 to 32 cores per chiplet. For AMD EPYC Venice, which can fit up to 8 chiplets, that opens the door to configurations of up to 96 Zen 6 cores or 256 Zen 6c cores.
L3 cache also takes a major leap. Again based on the data shared by AMD, a 12-core Zen 6 chiplet integrates 48 MB, compared with the 32 MB of the previous generation, and a 32-core Zen 6c chiplet goes up to 128 MB from the previous 32 MB. In practice, both designs land at 4 MB of L3 per core, and in Zen 6c’s case that means doubling the cache available per core compared with Zen 5c.
AMD maintains that Zen 6 isn’t just about higher core counts. The architecture, the company says, brings a wider execution window, improved branch prediction, and changes in the integer scheduler. It also adds full support for AVX-512 FP16, new Bit Matrix Multiply instructions, and four VNNI-INT8 pipelines instead of two. Both Zen 6 and Zen 6c keep SMT at 2 threads per core and the same base instruction set, at least based on the official information provided so far.
The AMD EPYC 9006 “Venice” platform also adds support for PCIe 6.0 and DDR5 MRDIMM memory of up to 12,800 MT/s. There will also be high-frequency models capable of reaching 5.3 GHz. In a data center, where memory and I/O bandwidth really matter, they’re improvements with a lot more runway than a spec table might suggest.
For PC, the most striking thing may not even be the IPC. AMD still hasn’t gone into detail with Zen 6 for Ryzen, but the move to a 12-core CCD could end up mattering more on desktop than the announcement suggests. A future 12-core Ryzen inside a single chiplet would avoid the inter-chiplet latency that current multi-CCD designs have, and that matters especially in latency-sensitive tasks, including games.
AMD hasn’t confirmed specifications, performance, prices, or a release date for those Ryzen chips. In the industry it’s more or less taken for granted that they’ll arrive later within the Ryzen 10000 family and under the codename “Olympic Ridge”, but that remains outside the scope of the official announcement, focused entirely on servers. Without concrete gaming tests or clear consumer details, that big IPC leap AMD is touting still needs quite a bit of context before it’s sold as an indisputable victory outside the data center.
So far, it’s not known when Zen 6-based Ryzen chips will reach the consumer market.
